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Dr.-Yuanyuan-Shi

Dr. Yuanyuan Shi is currently a Postdoctoral fellow (Funded by Marie Curie Fellowship from European Commission) at IMEC, Belgium. Her current research is mainly about developing wafer-scale two-dimensional (2D) materials based transistor technology for scaling high-performance logic devices beyond 3 nm technology node.

Dr. Shi received her Ph.D. degree in NanoScience with Excellent “Cum Laude” honor and Extraordinary PhD prize from the University of Barcelona in 2018. During her PhD, she was a visiting scholar at Stanford University for one year (2016-2017). Her PhD research work mainly focused on emerging memory devices, and its application for neuromorphic computing.

Dr. Shi has published more than 50 research articles (including Nature Electronics, IEDM, Nano Letters, Advanced Functional Materials etc.), two book chapters and granted for two international patents. She serves as an active member in IEEE EDS Nanotechnology committee and at the technical committee of several top conferences in the field of electronic devices, such as IEEE International Reliability Physics Symposium (IRPS), IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) and IEEE Electron Devices Technology and Manufacturing (EDTM). She is also an active reviewer for Nature, Nature Electronics, IEEE Electron Device Letters, Scientific Reports and many other journals.

Dr. Shi is a recipient of Marie Skłodowska-Curie Individual Fellowship (European Commission), IEEE EDS PhD student fellowship (three winners globally each year) and 2018 Chinese Government Award for Outstanding Self-Financed Students Abroad. She has been recognized as a Forbes 30 under 30 (one of the world’s most impactful community of young entrepreneurs and game-changers) in 2020 and also as one of the Rising Stars Women in Engineering in 2018.

1. Please summarize the research you do and explain why it is significant?

My research is focusing on developing wafer-scale two-dimensional (2D) materials-based transistor technology for scaling high-performance logic devices beyond 3 nm technology node. Internet of things and artificial intelligence demand further transistor performance improvements and devices size scaling. In a conventional planar silicon field effect transistor (FET), the gate controllability becomes weaker when its lateral dimension scales. Hence the transistor body thickness needs to be reduced to ensure efficient electrostatic control from the gate, which results in serve leakage current, saturation of the carrier mobility in the channel, channel hot-carrier degradation, and time-dependent dielectric breakdown and many other problems. Thanks to the atomic thickness, dangling bond-free surface and unique properties of 2D materials, theoretical studies have shown that these properties of 2D materials (mainly transition metal dichalcogenides, TMDs) can make them outperform Si as the channel material, enable the atomic-level scaling and excellent electrostatic gate control, decrease off-state power consumption and further extend Moore’s Law.

2. How might your research be used?

Introducing 2D materials in the structure of commercial electronic devices is challenging due to their complex synthesis and manipulation, which results that 2D materials are facing challenges to move towards industrialization. The applications of graphene, the best-known 2D material, and methods for its mass production are being developed through the European Commission’s €1-billion Graphene Flagship research program. However, other 2D materials are still largely in the academic phase. We are making efforts to achieve wafer-scale, uniform and single-crystalline growth of 2D materials, wafer-scale and clean transfer of 2D materials, and improvements to solve the specific issues (contact resistance, gate stacks, variability, reliability, yield, etc.) for large-area integration of 2D materials based nanoelectronics. Our research work will pave the way to large-area integration and industrialization of 2D materials-based transistors for beyond 3 nm technology node.

3. Why is the Park AFM important for your research?

Suitable technique to characterize the intrinsic physical and electrical properties of as-grown 2D materials, is a key link between the quality of as-grown 2D materials and the performance of 2D materials based electronic devices. This link can help us to better understand, control and improve the performance of 2D materials-based devices. However, the technique that can analyze the intrinsic electrical properties of as-grown 2D materials (without any transfer and patterning process) is extremely limited. Park AFM allows us to do multiple kinds of electrical scanning probe microscope (ESPM) characterizations including conductive atomic force microscope (CAFM), Kelvin probe force microscopy (KPFM) and others, directly on the surface of as-grown 2D materials without any patterning, which can combine electrical conductivity and work function of as-grown 2D materials with its topography. With the link of topography, we can also link the electrical properties of 2D materials with its physical properties (such as chemical composition). With all of this, it gives us comprehensive information of as-grown 2D materials and help us to evaluate the impact of these intrinsic properties on 2D materials based nanoelectronics.

4. What features of Park AFM are the most beneficial and why?

The Park NX-Hivac AFM can allow us to characterize the electrical properties of 2D materials in high vacuum (up to 10-6 torr). This is extremely important for our study since the TMDs can decay and get oxidized in ambient condition. We have performed experiments to compare the electrical properties of TMDs through CAFM characterization in ambient condition and in high vacuum, which shows that clear, homogeneous and higher currents (due to the removal of the water layer) signal are measured in high vacuum condition. Another beneficial feature of Park NX-Hivac AFM for us is that it allows to measure a large range of currents from picoamperes to milliamperes through using a logarithmic preamplifier.

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